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Embedded Memories for SoC: Overview of Design, Test, and Applications and Challenges in the Nano-Scale CMOS

Harold Pilo is a Senior Technical Staff member at IBM Systems and Technology Group. He will present “Embedded Memories for SoC: Overview of Design, Test, and Applications and Challenges in the Nano-Scale CMOS” at the International Solid-State Circuits Conference 2011 on Sunday 20th February in San Francisco.

The slides below form part of the presentation which includes:

  • A detailed description of the workhorse static memory, the 6T SRAM
  • Multi-port and content-addressable memories with special design considerations beyond the 6T cell
  • Embedded DRAM and its advantages in the SoC ecosystem
  • Special considerations for SOI memory design
  • State-of-the-art industry techniques that improve power and voltage scaling in the nanoscale regime
  • An overview of Built-In-Self-Test is provided.

Harold Pilo is a Senior Technical Staff member at IBM Systems and Technology Group. He joined IBM in 1993 to develop OEM SRAM products for the IT industry. He currently leads the circuit IP development for ASIC SRAM Technology Development. Prior to joining IBM, he worked at Motorola from 1989 to 1993. Harold has presented many papers at the ISSCC, VLSI and ITC. He holds over 50 US Patents and is currently a member of the ISSCC Memory Sub-committee. He graduated with a BSEE from the University of Florida in 1989.

About Harold Pilo

Harold Pilo
Harold Pilo is a Senior Technical Staff member at IBM Systems and Technology Group. He joined IBM in 1993 to develop OEM SRAM products for the IT industry. He currently leads the circuit IP development for ASIC SRAM Technology Development. Prior to joining IBM, he worked at Motorola from 1989 to 1993. Harold has presented many papers at the ISSCC, VLSI and ITC. He holds over 50 US Patents and is currently a member of the ISSCC Memory Sub-committee. He graduated with a BSEE from the University of Florida in 1989.

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